Ultra large scale integrated (ULSI) semiconductor devices, such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs), consist of multiple layers of conducting, semiconducting, and insulating materials, interconnected within and between layers in specific patterns designed to produce desired electronic functionalities. The materials are selectively patterned on each layer of the device, using lithographic techniques, typically by depositing one or more layers, patterning or masking the layers, and then etching the exposed portions of the materials.
Semiconductor device manufacturing is a very precise process, particularly as the size of the device structures continues to decrease and the complexity of the circuits continues to increase. Height differences, pitch and reflectivity variations and other imperfections present in the surface of underlying layers may compromise the formation of additional process layers and/or the ability to precisely position and dimension photoresist patterns formed during subsequent lithography processes.
A variety of methods have been developed in the art so as to increase the plurality of the layers during the manufacturing process. Such methods include reflow processes with deposited oxides, spin-on-glass (SOG) processes, etchback processes and Chemical-Mechanical Planarization (CMP) processes (also referred to as Chemical-Mechanical Polishing). CMP processes have been developed for removing a wide variety of materials including oxides, nitrides, suicides and metals from the surface of a semiconductor substrate. As used herein, the terms planarization and polishing are intended to be mutually inclusive terms for the same general category of processes.
A variety of different machine configurations have been developed for performing the various CMP processes. Machines used for CMP processing can be broadly grouped into either web-feed or fixed-pad categories. In both categories, however, the basic process uses a combination of a planarizing pad and a planarizing liquid to remove material from the surface of a semiconductor substrate using primarily mechanical action or through a combination of chemical and mechanical action.
The planarizing pads, in turn, can be broadly grouped into fixed-abrasive (FA) or non-abrasive (NA) categories. In fixed-abrasive pads, abrasive particles are distributed in material that forms at least a portion of the planarizing surface of the pad, while non-abrasive pad compositions do not include any abrasive particles. Because the fixed-abrasive pads already include abrasive particles, they are typically used in combination with a “clean” planarizing liquid that does not add additional abrasive particles.
With non-abrasive pads, however, substantially all of the abrasive particles used in the planarizing process are introduced as a component of the planarizing liquid, typically as a slurry applied to the planarizing surface of the pad. Both the “clean” and abrasive planarizing liquids can also include other chemical components, such as oxidizers, surfactants, viscosity modifiers, acids and/or bases in order to achieve the desired liquid properties for the removal of the targeted material layer from the semiconductor substrate and/or to provide lubrication for decreasing defectivity rates.
CMP processes typically utilize a combination of mechanical abrasion and chemical reaction(s) provided by the action of the planarizing slurry or planarizing liquid and a planarizing pad in order to remove one or more materials from a wafer surface and produce a substantially planar wafer surface. Planarizing slurries used in combination with non-abrasive pads, particularly for the removal of oxide layers, generally comprise a basic aqueous solution of a hydroxide, such as KOH, containing abrasive silica particles. Planarizing slurries, particularly for the removal of metal layers such as copper, generally comprise an aqueous solution of one or more oxidizers, such as hydrogen peroxide, to form the corresponding metal oxide that is then removed from the substrate surface.
The planarizing pads used in such processes typically comprise porous or fibrous materials, such as polyurethanes, that provide a relatively compliant surface onto which the planarizing slurry may be dispensed. The consistency of a CMP process may be greatly improved by automating the process so that the planarizing is terminated in response to a consistently measurable endpoint reflecting sufficient removal of an overlying material layer, typically followed by a brief “overetch” or “over-polish” to compensate for variations in the thickness of the material layer.
The size and concentration of the particles for planarizing a wafer surface can directly affect the resulting surface finish and the productivity of a CMP process. For example, if the abrasive particulate concentration is too low or the abrasive particle size too small, the material removal rate will generally slow and process throughput will be reduced. Conversely, if the abrasive particulate concentration is too high, the abrasive particles are too large or the abrasive particles begin to agglomerate, the wafer surface is more likely to be damaged, the CMP process may tend to become more variable and/or the material removal rate may decrease, resulting in reduced throughput, reduced yields or device reliability and/or increased scrap.
CMP processes may experience significant performance variations over time that further complicate processing of the wafers and reduce process throughput. In many cases, the performance variations may be attributable to changes in the characteristics of the planarizing pad as a result of the CMP process itself. Such changes may result from particulates agglomerating and/or becoming lodged in or hardening on the pad surface. Such changes may also be the result of wear, glazing or deformation of the pad, or simply the degradation of the pad material over time.
In a typical planarizing process, the planarizing machine brings the non-planar surface of a material layer formed over one or more patterns on a semiconductor substrate into contact with a planarizing surface of the planarizing pad. During the planarizing process, the surface of the planarizing pad will typically be continuously wetted with an abrasive slurry and/or a planarizing liquid to produce the desired planarizing surface. The substrate and/or the planarizing surface of the pad are then urged into contact and moved relative to one another to cause the planarizing surface to begin removing an upper portion of the material layer. This relative motion can be simple or complex and may include one or more lateral, rotational, revolving or orbital movements by the planarizing pad and/or the substrate in order to produce generally uniform removal of the material layer across the surface of the substrate.
As used herein, lateral movement is movement in a single direction, rotational movement is rotation about an axis through the center point of the rotating object, revolving movement is rotation of the revolving object about a non-centered axis and orbital movement is rotational or revolving movement combined with an oscillation. Although, as noted above, the relative motion of the substrate and the planarizing pad may incorporate different types of movement, the motion must typically be confined to a plane substantially parallel to the surface of substrate in order to achieve a planarized substrate surface.
Fixed abrasive pad types are known in the art of semiconductor wafer processing and have been disclosed in, for example, U.S. Pat. No. 5,692,950 to Rutherford et al.; U.S. Pat. No. 5,624,303 to Robinson; and U.S. Pat. No. 5,335,453 to Baldy et al. These types of fixed abrasive pads typically require a pre-conditioning cycle before they may be used in a CMP process, as well as periodic re-conditioning or in-situ surface conditioning during use, to generate a suitable number of asperities on the planarizing surface to maintain their planarizing ability.
The primary goal of CMP processing is to produce a defect-free planarized substrate surface having a material layer, or portions of a material layer, of uniform depth across the entire surface of the planarized substrate. Other goals, such as maximizing the throughput of the CMP process and reducing the per wafer cost, may, at times, conflict with the production of the best possible planarized surface. The uniformity of the planarized surfaces and the process throughput are directly related to the effectiveness and repeatability of the entire CMP process including the planarizing liquid, the planarizing pad, machine maintenance, as well as an array of other operating parameters. A variety of planarizing slurries and liquids have been developed that are somewhat specific to the composition of the material layer or layers that are to be removed and/or the composition of the planarizing pad being used. These tailored slurries and liquids are intended to provide adequate material removal rates and selectivity for particular CMP processes.
The benefits of CMP may be somewhat offset by the variations inherent in such a combination process, such as imbalances that may exist or may develop between the chemical and mechanical material removal rates of different material layers exposed on a single semiconductor substrate. Further, both the abrasive particles and other chemicals used in a typical CMP process may be relatively expensive and are generally unsuitable for reuse or recycling. This problem is compounded by the need to supply excess materials to the surface of the planarization pad to ensure that sufficient material is available at every point of the wafer surface as it moves across the pad. It is therefore desirable to reduce the quantity of abrasives and other chemicals used in a CMP process in order to reduce costs associated with both purchasing and storing the materials prior to use and the concerns and expense relating to the disposal of the additional waste materials.
A number of efforts toward reducing the variability and increasing the quality of CMP processes have been previously disclosed. For instance, U.S. Pat. No. 5,421,769 to Schultz et al. discloses a noncircular planarizing pad intended to compensate for variations resulting from the edges of a rotating wafer traveling across more of a planarizing pad than the interior surfaces. U.S. Pat. No. 5,441,598 to Yu et al. discloses a planarizing pad having a textured planarizing surface for providing a planarizing surface intended to provide more even polishing of wide and narrow structures across a wafer surface. U.S. Pat. No. 5,287,663 to Pierce et al. discloses a composite planarizing pad with a rigid layer opposite the planarizing surface and a resilient layer adjacent the rigid layer to reduce overplanarization, or “dishing,” of material from between harder underlying features. Each of the above references, in its entirety, is incorporated by reference in this disclosure.
Other prior art efforts to minimize uneven planarization of wafers have focused on forming additional material layers on the wafer surface to act as “stop” layers to control overplanarization. U.S. Pat. Nos. 5,356,513 and 5,510,652 to Burke et al. and U.S. Pat. No. 5,516,729 to Dawson et al. all provide additional material layers having an increased resistance to the CMP process under the layer being removed to protect the underlying circuit structures. These additional material layers, however, both complicate the semiconductor manufacturing process flow and, as recognized by Dawson et al., do not completely overcome the problem of “dishing.” Each of the above references, in its entirety, is incorporated by reference in this disclosure.
More recent efforts regarding planarizing pad compositions and constructions are disclosed in U.S. Pat. No. 6,425,815 B1 to Walker et al. (a dual material planarizing pad), U.S. Pat. No. 6,069,080 to James et al. (a fixed abrasive pad with a matrix material having specified properties), U.S. Pat. No. 6,454,634 B1 to James et al. (a multiphase self-dressing planarizing pad), WO 02/22309 A1 to Swisher et al. (a planarizing pad having particulate polymer in a cross-linked polymer binder), U.S. Pat. No. 6,368,200 B1 to Merchant et al. (a planarizing pad of a closed cell elastomer foam), U.S. Pat. No. 6,364,749 B1 to Walker (planarizing pad having polishing protrusions and hydrophilic recesses), U.S. Pat. No. 6,099,954 to Urbanavage et al. (elastomeric compositions with fine particulate matter) and U.S. Pat. No. 6,095,902 to Reinhardt (planarization pads manufactured from both polyester and polyether polyurethanes). Each of the above references, in its entirety, is incorporated by reference in this disclosure.
Conventional polishing of metallic and non-metallic substrates during the manufacture of semiconductor devices are typically conducted at downward pressures (also referred to as downforce) of at least about 3 psi (0.21 kg/cm2) and may range as high as 6 psi (0.42 kg/cm2) or more in order to achieve acceptable removal rates. However, although the increased downward pressure does result in increased removal rates, it also increases the likelihood of generating defects such as dishing, erosion and scratches in the wafers being polished, resulting in an increased scrap rate and a reduced yield rate for the wafers that survive the process. The increased downward pressure also tends to reduce the selectivity of the polish between different materials that may be present on the substrate being polished, thereby increasing the difficulty of completely removing the intended portion of the layer(s) without also removing a portion of the underlying layers as well. As noted above, this lack of selectively has led to the use of additional harder barrier or “stop” layers to protect the underlying structures, further complicating the manufacturing process to provide for the deposition and removal of these additional layers.